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128-macrocell max ? epld cy7c346 use ultra37000 tm for all new designs cypress semiconductor corporation ? 3901 north first street ? san jose , ca 95134 ? 408-943-2600 document #: 38-03005 rev. *b revised april 19, 2004 features ? 128 macrocells in eight logic array blocks (labs) ? 20 dedicated inputs, up to 64 bidirectional i/o pins ? programmable interconnect array ? 0.8-micron double-metal cmos eprom technology ? available in 84-pin clcc, plcc, and 100-pin pga, pqfp functional description the cy7c346 is an erasable programmable logic device (epld) in which cmos eprom cells are used to configure logic functions within the device. the max ? architecture is 100% user-configurable, allowi ng the device to accommodate a variety of independent logic functions. the 128 macrocells in the cy7c346 are divided into eight labs, 16 per lab. there are 256 expander product terms, 32 per lab, to be used and shared by the macrocells within each lab. each lab is interconnected through the programmable inter- connect array, allowing all signals to be routed throughout the chip. the speed and density of the cy7c346 allow it to be used in a wide range of applications, fr om replacement of large amounts of 7400-series ttl logic, to complex controllers and multifunction chips. with greater than 25 times the functionality of 20-pin plds, the cy7c346 allows the replacement of over 50 ttl devices. by replacing large amounts of logic, the cy7c346 reduces board space, part count, and increases system reliability. macrocell 49 macrocell 50 macrocell 51 macrocell 52 macrocell 53 macrocell 54 macrocell 55 macrocell 56 macrocell 33 macrocell 34 macrocell 35 macrocell 36 macrocell 37 macrocell 38 macrocell 39 macrocell 40 macrocell 104 macrocell 103 macrocell 102 macrocell 101 macrocell 100 macrocell 99 macrocell 98 macrocell 97 macrocell 120 macrocell 119 macrocell 118 macrocell 117 macrocell 116 macrocell 115 macrocell 114 macrocell 113 macrocell 1 macrocell 2 macrocell 3 macrocell 4 macrocell 5 macrocell 6 macrocell 7 macrocell 8 macrocell 17 macrocell 18 macrocell 19 macrocell 20 macrocell 21 macrocell 22 macrocell 23 macrocell 24 logic block diagram macrocell 88 macrocell 87 macrocell 86 macrocell 85 macrocell 84 macrocell 83 macrocell 82 macrocell 81 macrocell 121?128 macrocell 105?112 macrocell 86?96 macrocell 41?48 macrocell 25?32 macrocell 9?16 system clock p i a input [59] (n4) 36 . input [60] (m5) 37 . input [61] (n5) 38 . input [64] (n6) 41 . input [65] (m7) 42 . input [66] (l7) 43 . input [67] (n7) 44 . input [70] (l8) 47 . input [71] (n9) 48 . input [72] (m9) 49 . [100] (c13) nc [99] (d12) nc [98] (d13) 77 [97] (e12) 76 [96] (e13) 75 [95] (f11) 74 [92] (g13) 73 [91] (g11) 72 [90] (g12) nc [89] (h13) nc [86] (j13) 71 [85] (j12) 70 [84] (k13) 69 [83] (k12) 68 [82] (l13) 67 [81] (l12) 64 [80] (m13) nc [79] (m12) nc [78] (n13) 63 [77] (m11) 60 [76] (n12) 59 [75] (n11) 58 [74] (m10) 57 [73] (n10) 56 [58] (m4) nc [57] (n3) nc [56] (m3) 55 [55] (n2) 54 [54] (m2) 53 [53] (n1) 52 [52] (l2) 51 [51] (m1) 50 8 (b13) [1] 9(c12) [2] 10 (a13) [3] 11 (b12) [4] 12 (a12) [5] 13 (11) [6] nc (a11) [7] nc (b10) [8] 14 (a4) [23] 15 (b4) [24] 16 (a3) [25] 17 (a2) [26] 18 (b3) [27] 21 (a1) [28] nc (b2) [29] nc (b1) [30] 22 (c2) [31] 25 (c1) [32] 26 (d2) [33] 27 (d1) [34] 28 (e2) [35] 29 (e1) [36] nc (f1) [39] nc (g2) [40] 30 (g3) [41] 31 (g1) [42] 32 (h3) [45] 33 (j1) [46] 34 (j2) [47] 35 (k1) [48] nc (k2) [49] nc (l1) [50] lab h lab g lab f lab e lab a lab b lab c lab d 3, 20, 37, 54 (a6,b6,f12,f13,h1,h2,m8,n8) [18, 19, 43, 44, 68, 69, 93, 94] 16, 33, 50, 67 (b8,c8,f2,f3,h11,h12,l6,m6) [12, 13, 37, 38, 62, 63, 87, 88] v cc gnd () ? pertain to 100-pin pga package 1 (c7) [16] input/clk .. 78 (a10) [9] input . ..... 79 (b9) [10] input . ..... 80 (a9) [11] input ..... 83 (a8) [14] input . ..... 84 (b7) [15] input . ..... 2 (a7) [17] input .. ..... 5 (c6) [20] input .. ..... 6 (a5) [21] input .. ..... 7 (b5) [22] input .. ..... macrocell 73? 80 macrocell 72 macrocell 71 macrocell 70 macrocell 69 macrocell 68 macrocell 67 macrocell 66 macrocell 65 macrocell 57? 64 [ ] ?pertain to 100-pin pqfp package .
cy7c346 use ultra37000 tm for all new designs document #: 38-03005 rev. *b page 2 of 21 selection guide 7c346-25 7c346-30 7c346-35 unit maximum access time 25 30 35 ns maximum operating current commercial 250 250 250 ma military 325 320 320 industrial 320 320 320 maximum standby current commercial 225 225 225 ma military 275 275 275 industrial 275 275 275 pin configurations i/o top view plcc/clcc 7 64 53 11 12 10 98 43 42 44 45 46 21 22 24 23 25 13 14 41 40 21 26 27 18 19 17 16 15 20 28 29 31 30 32 33 36 35 37 38 39 34 52 51 49 50 48 47 53 54 55 60 58 59 57 56 66 65 63 64 62 67 61 input/clk i/o i/o i/o v cc inp /clk inp gnd i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o v cc inp gnd inp i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o pga bottom view cy7c346 inp inp i/o i/o i/o i/o i/o i/o l k j h g f e d c b a 1234567 91011 i/o i/o i/o inp 8 i/o i/o i/o i/o i/o i/o i/o v cc 12 13 n m inp i/o inp inp inp i/o i/o gnd gnd v cc v cc i/o i/o i/o inp gnd i/o i/o v cc v cc gnd gnd i/o i/o i/o inp gnd inp i/o inp inp i/o inp v cc inp inp inp 74 73 72 71 70 69 68 84 83 82 81 80 79 78 77 76 75 input input v cc v cc input input input i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o gnd gnd i/o i/o v cc v cc i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o input input input gnd gnd input input input input v cc v cc input input input i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o v cc v cc i/o i/o gnd gnd i/o i/o i/o i/o i/o i/o i/o input gnd gnd input input input i/o i/o i/o cy7c346
cy7c346 use ultra37000 tm for all new designs document #: 38-03005 rev. *b page 3 of 21 pin configurations (continued) top view pqfp 72 71 69 70 68 2 3 1 36 35 12 13 15 14 16 4 5 34 33 67 66 17 26 9 10 8 7 6 11 27 28 30 29 31 32 61 60 58 59 57 65 64 56 i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o input i/o input v cc v cc input input input i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o input input input 62 63 i/o i/o i/o gnd i/o gnd gnd i/o i/o v input input i/o i/o gnd gnd input input input i/o i/o i/o i/o v cc v cc input input input i/o i/o i/o i/o i/o i/o 18 19 20 21 22 23 24 25 55 54 53 52 51 50 49 48 47 46 45 37 38 39 40 41 42 43 cc 44 80 79 77 78 76 75 74 73 95 96 97 98 100 99 81 82 83 84 85 86 94 93 92 91 90 89 88 87 i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o input gnd gnd input input/clk input i/o gnd v cc i/o i/o i/o v cc i/o i/o i/o v cc cy7c346
cy7c346 use ultra37000 tm for all new designs document #: 38-03005 rev. *b page 4 of 21 logic array blocks there are eight logic array blocks in the cy7c346. each lab consists of a macrocell array containing 16 macrocells, an expander product term array containing 32 expanders, and an i/o block. the lab is fed by the programmable interconnect array and the dedicated input bus. all macrocell feedbacks go to the macrocell array, the expander array, and the program- mable interconnect array. expanders feed themselves and the macrocell array. all i/o feedb acks go to the programmable interconnect array so that they may be accessed by macro- cells in other labs as well as the macrocells in the lab in which they are situated. externally, the cy7c346 provides 20 dedicated inputs, one of which may be used as a system clock. there are 64 i/o pins that may be individually configured for input, output, or bidirec- tional data flow. programmable interconnect array the programmable interconnec t array (pia) solves inter- connect limitations by routing only the signals needed by each logic array block. the inputs to the pia are the outputs of every macrocell within the device and the i/o pin feedback of every pin on the device. timing delays timing delays within the cy7c346 may be easily determined using warp ? , warp professional?, or warp enterprise? software. the cy7c346 has fixed internal delays, allowing the user to determine the worst case timing delays for any design. design recommendations operation of the devices de scribed herein with conditions above those listed under ?maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicate d in the operational sections of this data sheet is not implied. exposure to absolute maximum ratings conditions for extended periods of time may affect device reliability. the cy7c346 contains circuitry to protect device pins from high static voltages or electric fields, but normal precautions should be taken to avoid application of any voltage higher than the maximum rated voltages. for proper operation, i nput and output pins must be constrained to the range gnd (v in or v out ) v cc . unused inputs must always be tied to an appropriate logic level (either v cc or gnd). each set of v cc and gnd pins must be connected together directly at the device. power supply decoupling capacitors of at least 0.2 f must be connected between v cc and gnd. for the most effective decoupling, each v cc pin should be separately decoupled to gnd directly at the device. decoup ling capacitors should have good frequency response, such as monolithic ceramic types have. design security the cy7c346 contains a programmable design security feature that controls the access to the data programmed into the device. if this programmable feature is used, a proprietary design implemented in the device cannot be copied or retrieved. this enables a high level of design control to be figure 1. cy7c346 internal timing model logic array control delay t lac expander delay t exp clock delay t ic t rd t comb t latch input delay t in register output delay t od t xz t zx logic array delay t lad feedback delay t fd output input system clock delay t ics t rh t rsu t pre t clr pia delay t pia i/o delay t io
cy7c346 use ultra37000 tm for all new designs document #: 38-03005 rev. *b page 5 of 21 obtained since programmed data within eprom cells is invisible. the bit that controls this function, along with all other program data, may be reset simply by erasing the entire device. the cy7c346 is fully functionally tested and guaranteed through complete testing of each programmable eprom bit and all internal logic elements thus ensuring 100% programming yield. the erasable nature of these devices allows test programs to be used and erased during early stages of the production flow. the devices also contain on-board logic test circuitry to allow verification of function and ac specification once encapsu- lated in non-windowed packages. timing considerations unless otherwise stated, propagation delays do not include expanders. when using expanders, add the maximum expander delay t exp to the overall delay. similarly, there is an additional t pia delay for an input from an i/o pin when compared to a signal from straight input pin. when calculating synchronous frequencies, use t s1 if all inputs are on dedicated input pins. the parameter t s2 should be used if data is applied at an i/o pin. if t s2 is greater than t co1 , 1/t s2 becomes the limiting frequency in the data path mode unless 1/(t wh + t wl ) is less than 1/t s2 . when expander logic is used in the data path, add the appro- priate maximum expander delay, t exp to t s1 . determine which of 1/(t wh + t wl ), 1/t co1 , or 1/(t exp + t s1 ) is the lowest frequency. the lowest of these frequencies is the maximum data path frequency for the synchronous configuration. when calculating external asynchronous frequencies, use t as1 if all inputs are on the dedicated input pins. if any data is applied to an i/o pin, t as2 must be used as the required set-up time. if (t as2 + t ah ) is greater than t aco1 , 1/(t as2 + t ah ) becomes the limiting frequency in the data path mode unless 1/(t awh + t awl ) is less than 1/(t as2 + t ah ). when expander logic is used in the data path, add the appro- priate maximum expander delay, t exp to t as1 . determine which of 1/(t awh + t awl ), 1/t aco1 , or 1/(t exp + t as1 ) is the lowest frequency. the lowest of these frequencies is the maximum data path frequency for the asynchronous config- uration. the parameter t oh indicates the system compatibility of this device when driving other synchronous logic with positive input hold times, which is controlled by the same synchronous clock. if t oh is greater than the minimum required input hold time of the subsequent synchronous logic, then the devices are guaranteed to function properly with a common synchronous clock under worst-case environmental and supply voltage conditions. the parameter t aoh indicates the system compatibility of this device when driving subsequent registered logic with a positive hold time and using the same asynchronous clock as the cy7c346. in general, if t aoh is greater than the minimum required input hold time of the subsequent logic (synchronous or asynchronous) then the devices are guaranteed to function properly under worst-case environmental and supply voltage conditions, provided the clock signal source is the same. this also applies if expander lo gic is used in the clock signal path of the driving device, but not for the driven device. this is due to the expander logic in the second device?s clock signal path adding an additional delay (t exp ) causing the output data from the preceding device to change prior to the arrival of the clock signal at the following device?s register. typical i cc vs. f max output drive current 400 300 200 100 1 khz 10 khz 100 khz 1 mhz i cc maximum frequency 10 mhz 0 50 mhz 100 hz active (ma) typ. v cc = 5.0v room temp. 01 2 3 4 i output current (ma) typical v o output voltage (v) 100 80 60 40 20 5 o i oh i ol v cc = 5.0v room temp. 0.45
cy7c346 use ultra37000 tm for all new designs document #: 38-03005 rev. *b page 6 of 21 maximum ratings (above which the useful life may be impaired. for user guide- lines, not tested.) storage temperature ................................. ?65 c to+150 c ambient temperature with power applied............................................. ?55 c to+125 c maximum junction temperature (under bias).................................................................. 150 c supply voltage to ground potential ............... ?2.0v to +7.0v maximum power dissipation...................................2500 mw dc v cc or gnd current ............................................500 ma dc output current per pin ...................... ?25 ma to +25 ma dc input voltage [1] .........................................?3.0v to +7.0v dc program voltage..................................................... 13.0v static discharge voltage........................................... > 1100v (per mil-std-883, method 3015) operating range range ambient temperature v cc commercial 0 c to +70 c 5v 5% industrial ?40 c to +85 c 5v 10% military ?55 c to +125 c (case) 5v 10% electrical characteristics over the operating range [2] parameter description test conditions min. max. unit v oh output high voltage v cc = min., i oh = ?4.0 ma 2.4 v v ol output low voltage v cc = min., i ol = 8.0 ma 0.45 v v ih input high voltage 2.2 v cc + 0.3 v v il input low voltage ?0.3 0.8 v i ix input current gnd < v in < v cc ?10 +10 a i oz output leakage current v o = v cc or gnd ?40 +40 a i os output short circuit current v cc = max., v out = 0.5v [3, 4] ?30 ?90 ma i cc1 power supply current (standby) v i = gnd (no load) commercial 225 ma military/industrial 275 i cc2 power supply current [5] v i = v cc or gnd (no load) f = 1.0 mhz [4] commercial 250 ma military/industrial 320 t r recommended input rise time 100 ns t f recommended input fall time 100 ns capacitance [6] parameter description test conditions max. unit c in input capacitance v in = 2v, f = 1.0 mhz 10 pf c out output capacitance v out = 2v, f = 1.0 mhz 20 pf ac test loads and waveforms [6] notes: 1. minimum dc input is ?0.3v. during transitions, the inputs may undershoot to ?3.0v for periods less than 20 ns. 2. typical values are for t a = 25c and v cc = 5v. 3. not more than one output should be tested at a time. duration of the short circuit should not be more than one second. v out = 0.5v has been chosen to avoid test problems caused by tester ground degradation. 4. guaranteed by design but not 100% tested. 5. this parameter is measured with device pr ogrammed as a 16-bit counter in each lab. 6. part (a) in ac test load and waveforms is used for all parameters except t er and t xz , which is used for part (b) in ac test load and waveforms. all external timing parameters are measured referenc ed to external pins of the device. 3.0v 5v output r1 464 ? r2 250 ? 50 pf including jig and scope gnd 90% 10% 90% 10% 6ns 6 ns 5v output r1 464 ? r2 250 ? 5pf including jig and scope (a) (b) output 1.75v equivalent to: thvenin equival ent (commercial/military) all input pulses 163 ?
cy7c346 use ultra37000 tm for all new designs document #: 38-03005 rev. *b page 7 of 21 commercial and industrial external synchronous switching characteristics [6] over operating range parameter description 7c346-25 7c346-30 7c346-35 unit min. max. min. max. min. max. t pd1 dedicated input to combinatorial output delay [7] 25 30 35 ns t pd2 i/o input to combinat orial output delay [10] 40 45 55 ns t pd3 dedicated input to combinatoria l output delay with expander delay [11] 37 44 55 ns t pd4 i/o input to combinatorial ou tput delay with expander delay [4, 12] 52 59 75 ns t ea input to output enable delay [4, 7] 25 30 35 ns t er input to output disable delay [4, 7] 25 30 35 ns t co1 synchronous clock input to output delay 14 16 20 ns t co2 synchronous clock to local feedback to combinatorial output [4, 13] 30 35 42 ns t s1 dedicated input or feedback set-up time to synchronous clock input [7, 14] 15 20 25 ns t s2 i/o input set-up time to synchronous clock input [7] 30 36 45 ns t h input hold time from synchronous clock input [7] 0 0 0 ns t wh synchronous clock input high time 8 10 12.5 ns t wl synchronous clock input low time 8 10 12.5 ns t rw asynchronous clear width [4, 7] 25 30 35 ns t rr asynchronous clear recovery time [4, 7] 25 30 35 ns t ro asynchronous clear to registered output delay [7] 25 30 35 ns t pw asynchronous preset width [4, 7] 25 30 35 ns t pr asynchronous preset recovery time [4, 7] 25 30 35 ns t po asynchronous preset to registered output delay [7] 25 30 35 ns t cf synchronous clock to local feedback input [4, 15] 3 3 6 ns t p external synchronous clock period (1/(f max3 ) [4] 16 20 25 ns f max1 external feedback maximum frequency (1/(t co1 + t s1 )) [4, 16] 34.5 27.7 22.2 mhz f max2 internal local feedback maximum frequency, lesser of (1/(t s1 + t cf )) or (1/t co1 ) [4, 17] 55.5 43.4 32.2 mhz f max3 data path maximum frequency, lesser of (1/(t wl + t wh )), (1/(t s1 + t h )) or (1/t co1 ) [4, 18] 62.5 50 40 mhz f max4 maximum register toggle frequency (1/(t wl + t wh ) [4, 19] 62.5 50 40 mhz t oh output data stable time from synchronous clock input [4, 20] 3 3 3 ns notes: 7. this specification is a measure of the del ay from input signal applied to a dedicated input (68-pin plcc input pin 1, 2, 32, 34, 35, 66, or 68) to combinatorial output on any output pin. this delay assumes no expander terms are used to form the logic function. 8. when this note is applied to any parameter specification it i ndicates that the signal (data, asynchronous clock, asynchronous clear, and/or asynchronous preset) is applied to a dedicated input only and no signal path (either clock or data) employs expander logic. 9. if an input signal is applied to an i/o pin an additional delay equal to tpia should be added to the comparable delay for a d edicated input. if expanders are used, add the maximum expander delay texp to the overall delay for the comparable delay without expanders. 10. this specification is a measure of the delay from input signal applied to an i/o macrocell pin to any output. this delay ass umes no expander terms are used to form the logic function. 11. this specification is a measure of the delay from an input signal applied to a dedicated input (68-pin plcc input pin 1, 2, 32, 34, 35, 36, 66, or 68) to combinatorial output on any output pin. this delay assumes expander terms ar e used to form the logic function and includes the worst-case exp ander logic delay for one pass through the expander logic. 12. this specification is a measure of the delay from an input si gnal applied to an i/o macrocell pin to any output. this delay assumes expander terms are used to form the logic function and includes the worst-case expander logi c delay for one pass through the expander logic. this paramete r is tested periodically by sampling production material. 13. this specification is a measure of the de lay from synchronous register clock to internal feedback of the register output sig nal to the input of the lab logic array and then to a combinatorial output. this delay assumes no exp anders are used, register is synchronously clocked and all feedbac k is within the same lab. this parameter is tested periodically by sampling production material. 14. if data is applied to an i/o input for capture by a macrocell register, the i/o pin input set-up time minimums should be obs erved. these parameters are ts2 for synchronous operation and tas2 for asynchronous operation. 15. this specification is a measure of the delay associated with t he internal register feedback path. this is the delay from syn chronous clock to lab logic array input. this delay plus the register set-up time, ts1, is the mi nimum internal period for an internal synchronous state machine configuration. this delay is for feedback within the same lab. this parameter is te sted periodically by sampling production material. 16. this specification indicates the guaranteed maximum frequency, in synchronous mode, at which a state machine configuration w ith external feedback can operate. it is assumed that all data inputs and exte rnal feedback signals are applied to dedicated inputs. 17. this specification indicates the guaranteed maximum frequency at which a state machine with internal-only feedback can opera te. if register output states must also control external points, this frequency can still be observ ed as long as this frequency is less than 1/tco1. all feedback is assumed to be local originating within the same lab. 18. this frequency indicates the maximum frequency at which the device may operate in data path mode (dedicated input pin to out put pin). this assumes data input signals are applied to dedicated input pins and no expander logic is used. if any of the data inputs are i/o pins, ts2 is the appropriate ts for calculation. 19. this specification indicates the guaranteed maximum frequency, in synchronous mode, at which an individual output or buried register can be cycled by a clock signal applied to the dedicated clock input pin. 20. this parameter indicates the minimum time after a synchronous register clock input that the previous register output data is maintained on the output pin.this specification is a measure of the delay from an asynchronous register clock input to internal feedback of the register output s ignal to the input of the lab logic array and then to a combinatorial output. this delay assumes no expanders are used in the logic of combinatorial output or the asynchronous clock input. the clock signal is applied to the dedicated clock input pin and all feedback is within a single lab. this parameter is tested peri odically by sampling production material.
cy7c346 use ultra37000 tm for all new designs document #: 38-03005 rev. *b page 8 of 21 commercial and industrial external asynchronous switching characteristics [6] over operating range parameter description 7c346-25 7c346-30 7c346-35 unit min. max. min. max. min. max. t aco1 asynchronous clock input to output delay [7] 25 30 35 ns t aco2 asynchronous clock input to local feedback to combinatorial output [20] 39 46 55 ns t as1 dedicated input or feedback set-up time to asynchronous clock input [7] 5 6 8 ns t as2 i/o input set-up time to asynchronous clock input [7] 19 22 28 ns t ah input hold time from asynchronous clock input [7] 6 8 10 ns t awh asynchronous clock input high time [7] 11 14 16 ns t awl asynchronous clock input low time [7, 21] 9 11 14 ns t acf asynchronous clock to local feedback input [4, 22] 15 18 22 ns t ap external asynchronous clock period (1/(f maxa4 )) [4] 20 25 30 ns f maxa1 external feedback maximum frequency in asynchronous mode (1/(t aco1 + t as1 )) [4, 23] 33.3 27.7 23.2 mhz f maxa2 maximum internal asynchronous frequency [4, 24] 50 40 33.3 mhz f maxa3 data path maximum frequency in asynchronous mode [4, 25] 40 33.3 28.5 mhz f maxa4 maximum asynchronous register toggle frequency 1/(t awh + t awl ) [4, 26] 50 40 33.3 mhz t aoh output data stable time from asynchronous clock input [4, 27] 15 15 15 ns notes: 21. this parameter is measured with a positive-edge triggered cloc k at the register. for negative edge triggering, the tawh and tawl parameters must be swapped. if a given input is used to clock multiple registers with both positive and negative polarity, tawh should be used for both taw h and tawl. 22. this specification is a measure of the delay associated with th e internal register feedback path for an asynchronous clock t o lab logic array input. this delay plus the asynchronous register set-up time , tas1, is the minimum internal period for an internal asynchronously clocked state m achine configuration. this delay is for feedback within the same lab, assumes no expander logic in the clock path, and assumes that the clock input signal is ap plied to a dedicated input pin. this parameter is tested periodically by sampling production material. 23. this specification indicates the guaranteed maximum frequency at which an asynchronously clocked state machine configuration with external feedback can operate. it is assumed that all data inputs, clock inputs, and feedback signals are applied to dedicated inputs and that no exp ander logic is employed in the clock signal path or data path. 24. this specification indicates the guaranteed maximum frequency at which an asynchronously clocked state machine with internal -only feedback can operate. this parameter is determined by the lesser of (1/(t acf + t as1 )) or (1/(t awh + t awl )). if register output states must also control external points, this frequency can still be observed as long as this frequency is less than 1/t aco1 . this specification assumes no expander logic is utilized, all data inputs and clock inputs are applied to dedicated inputs, and all state feedback is within a single lab. this parameter is tested periodically by sampling production material. 25. this frequency is the maximum frequency at which the device may operate in the asynchronously clocked data path mode. this s pecification is determined by the lesser of 1/(t awh + t awl ), 1/(t as1 + t ah ) or 1/t aco1 . it assumes data and clock input signals are applied to dedicated input pins and no expander logic is used. 26. this specification indicates the guaranteed maximum frequency at which an individual output or buried register can be cycled in asynchronously clocked mode by a clock signal applied to an external dedicated input pin. 27. this parameter indicates the minimum time that the previous register output data is maintained on the output after an asynch ronous register clock input applied to an external dedicated input pin.
cy7c346 use ultra37000 tm for all new designs document #: 38-03005 rev. *b page 9 of 21 commercial and industrial internal switching characteristics over operating range parameter description 7c346-25 7c346-30 7c346-35 unit min. max. min. max. min. max. t in dedicated input pad and buffer delay 5 7 9 ns t io i/o input pad and buffer delay 6 6 9 ns t exp expander array delay 12 14 20 ns t lad logic array data delay 12 14 16 ns t lac logic array control delay 10 12 13 ns t od output buffer and pad delay 5 5 6 ns t zx output buffer enable delay [28] 10 11 13 ns t xz output buffer disable delay 10 11 13 ns t rsu register set-up ti me relative to clock signal at register 6 8 10 ns t rh register hold time relative to clock signal at register 6 8 10 ns t latch flow through latch delay 3 4 4 ns t rd register delay 1 2 2 ns t comb transparent mode delay [29] 3 4 4 ns t ch clock high time 8 10 12.5 ns t cl clock low time 8 10 12.5 ns t ic asynchronous clock logic delay 14 16 18 ns t ics synchronous clock delay 1 1 1 ns t fd feedback delay 1 1 2 ns t pre asynchronous register preset time 5 6 7 ns t clr asynchronous register clear time 5 6 7 ns t pcw asynchronous preset and clear pulse width 5 6 7 ns t pcr asynchronous preset and clear recovery time 5 6 7 ns t pia programmable interconnect array delay time 14 16 20 ns notes: 28. sample tested only for an output change of 500 mv. 29. this specification guarantees the maximum combinatorial delay associated with the macrocell register bypass when the macroce ll is configured for combinatorial operation.
cy7c346 use ultra37000 tm for all new designs document #: 38-03005 rev. *b page 10 of 21 military external synchronous switching characteristics [6] over operating range parameter description 7c346-30 7c346-35 unit min. max. min. max. t pd1 dedicated input to combinatorial output delay [7] 30 35 ns t pd2 i/o input to combinat orial output delay [10] 45 55 ns t pd3 dedicated input to combinatorial output delay with expander delay [11] 44 55 ns t pd4 i/o input to combinator ial output delay with expander delay [4, 12] 59 75 ns t ea input to output enable delay [4, 7] 30 35 ns t er input to output disable delay [4, 7] 30 35 ns t co1 synchronous clock input to output delay 16 20 ns t co2 synchronous clock to local feedback to combinatorial output [4, 13] 35 42 ns t s1 dedicated input or feedback set-up time to synchronous clock input [7, 14] 20 25 ns t s2 i/o input set-up time to synchronous clock input [7] 36 45 ns t h input hold time from synchronous clock input [7] 0 0 ns t wh synchronous clock input high time 10 12.5 ns t wl synchronous clock input low time 10 12.5 ns t rw asynchronous clear width [4, 7] 30 35 ns t rr asynchronous clear recovery time [4, 7] 30 35 ns t ro asynchronous clear to registered output delay [7] 30 35 ns t pw asynchronous preset width [4, 7] 30 35 ns t pr asynchronous preset recovery time [4, 7] 30 35 ns t po asynchronous preset to registered output delay [7] 30 35 ns t cf synchronous clock to local feedback input [4, 15] 3 6 ns t p external synchronous clock period (1/(f max3 )) [4] 20 25 ns f max1 external feedback maximum frequency (1/(t co1 + t s1 )) [4, 16] 27.7 22.2 mhz f max2 internal local feedback maximum frequency, lesser of (1/(t s1 + t cf )) or (1/t co1 ) [4, 17] 43.4 32.2 mhz f max3 data path maximum frequency, lesser of (1/(t wl + t wh )), (1/(t s1 + t h )) or (1/t co1 ) [4, 18] 50 40 mhz f max4 maximum register toggle frequency (1/(t wl + t wh )) [4, 19] 50 40 mhz t oh output data stable time from synchronous clock input [4, 20] 3 3 ns
cy7c346 use ultra37000 tm for all new designs document #: 38-03005 rev. *b page 11 of 21 military external asynchronous switching characteristics [6] over operating range parameter description 7c346-30 7c346-35 unit min. max. min. max. t aco1 asynchronous clock input to output delay [7] 30 35 ns t aco2 asynchronous clock input to local feedback to combinatorial output [20] 46 55 ns t as1 dedicated input or feedback set-up time to asynchronous clock input [7] 6 8 ns t as2 i/o input set-up time to asynchronous clock input [7] 22 28 ns t ah input hold time from asynchronous clock input [7] 8 10 ns t awh asynchronous clock input high time [7] 14 16 ns t awl asynchronous clock input low time [7, 21] 11 14 ns t acf asynchronous clock to local feedback input [4, 22] 18 22 ns t ap external asynchronous clock period (1/(f maxa4 )) [4] 25 30 ns f maxa1 external feedback maximum frequency in asynchronous mode (1/(t aco1 + t as1 )) [4, 23] 27.7 23.2 mhz f maxa2 maximum internal asynchronous frequency [4, 24] 40 33.3 mhz f maxa3 data path maximum frequency in asynchronous mode [4, 25] 33.3 28.5 mhz f maxa4 maximum asynchronous register toggle frequency 1/(t awh + t awl ) [4, 26] 40 33.3 mhz t aoh output data stable time from asynchronous clock input [4, 27] 15 15 ns
cy7c346 use ultra37000 tm for all new designs document #: 38-03005 rev. *b page 12 of 21 military typical internal switching characteristics over operating range parameter description 7c346-30 7c346-35 unit min. max. min. max. t in dedicated input pad and buffer delay 7 9 ns t io i/o input pad and buffer delay 6 9 ns t exp expander array delay 14 20 ns t lad logic array data delay 14 16 ns t lac logic array control delay 12 13 ns t od output buffer and pad delay 5 6 ns t zx output buffer enable delay [28] 11 13 ns t xz output buffer disable delay 11 13 ns t rsu register set-up time relative to clock signal at register 8 10 ns t rh register hold time relative to clock signal at register 8 10 ns t latch flow through latch delay 4 4 ns t rd register delay 2 2 ns t comb transparent mode delay [29] 4 4 ns t ch clock high time 10 12.5 ns t cl clock low time 10 12.5 ns t ic asynchronous clock logic delay 16 18 ns t ics synchronous clock delay 2 3 ns t fd feedback delay 1 2 ns t pre asynchronous register preset time 6 7 ns t clr asynchronous register clear time 6 7 ns t pcw asynchronous preset and clear pulse width 6 7 ns t pcr asynchronous preset and clear recovery time 6 7 ns t pia programmable interconnect array delay time 16 20 ns
cy7c346 use ultra37000 tm for all new designs document #: 38-03005 rev. *b page 13 of 21 switching waveforms external combinatorial t pd1 /t pd2 t er t ea valid output dedicated input/ i/o input combinatorial output combinatorial or registered output high-impedance three-state high-impedance three-state [10] [7] [7] [7] external synchronous t h t s1 t wh t wl t rr /t pr t rw /t pw t oh t co1 t ro /t po t co2 dedicated inputs or registered feedback synchronous clock asynchronous clear/preset registered outputs combinatorial output from registered feedback [7] [7] [7] external asynchronous t aco1 t ah t as1 t awh t awl t rr /t pr t rw /t pw t aoh t ro /t po t aco2 asynchronous clock input asynchronous registered outputs dedicated inputs or registered feedback asynchronous clear/preset combinatorial output from asynchronous registered feedback
cy7c346 use ultra37000 tm for all new designs document #: 38-03005 rev. *b page 14 of 21 switching waveforms (continued) internal combinatorial t in t io t pia t exp t lac ,t lad input pin expander i/o pin logic array array delay output logic array input internal asynchronous t io t awh t awl t f t in t ic t rsu t rh t rd ,t latch t fd t clr ,t pre t fd clock pin logic array logic array clock from data from clock into logic array register output to another lab t pia to local lab register output logic array t r internal synchronous t ch t cl t in t ics t rsu t rh system cl ock pin system cl ock at register data from logic array
cy7c346 use ultra37000 tm for all new designs document #: 38-03005 rev. *b page 15 of 21 switching waveforms (continued) internal synchronous t xz t zx t od high impedance clock from logic array logic array data from output pin t rd state
cy7c346 use ultra37000 tm for all new designs document #: 38-03005 rev. *b page 16 of 21 military specifications group a subgroup testing dc characteristics parameter subgroups v oh 1, 2, 3 v ol 1, 2, 3 v ih 1, 2, 3 v il 1, 2, 3 i ix 1, 2, 3 i oz 1, 2, 3 i cc1 1, 2, 3 switching characteristics parameter subgroups t pd1 7, 8, 9, 10, 11 t pd2 7, 8, 9, 10, 11 t pd3 7, 8, 9, 10, 11 t co1 7, 8, 9, 10, 11 t s1 7, 8, 9, 10, 11 t s2 7, 8, 9, 10, 11 t h 7, 8, 9, 10, 11 t wh 7, 8, 9, 10, 11 t wl 7, 8, 9, 10, 11 t ro 7, 8, 9, 10, 11 t po 7, 8, 9, 10, 11 t aco1 7, 8, 9, 10, 11 t aco2 7, 8, 9, 10, 11 t as1 7, 8, 9, 10, 11 t ah 7, 8, 9, 10, 11 t awh 7, 8, 9, 10, 11 t awl 7, 8, 9, 10, 11 ordering information speed (ns) ordering code package name package type operating range 25 cy7c346-25hc/hi h84 84-pin windowed leaded chip carrier commercial/industrial cy7c346-25jc/ji j83 84-lead plastic leaded chip carrier cy7c346-25nc/ni n100 100-lead plastic quad flatpack cy7c346-25rc/ri r100 100-pin windowed ceramic pin grid array 30 cy7c346-30hc/hi h84 84-pin windowed leaded chip carrier commercial/industrial cy7c346-30jc/ji j83 84-lead plastic leaded chip carrier cy7c346-30nc/ni n100 100-lead plastic quad flatpack cy7c346-30hmb h84 84-pin windowed leaded chip carrier military cy7c346-30rmb r100 100-pin windowed ceramic pin grid array
cy7c346 use ultra37000 tm for all new designs document #: 38-03005 rev. *b page 17 of 21 35 cy7c346-35jc/ji j83 84-lead plastic leaded chip carrier commercial/industrial cy7c346-35nc/ni n100 100-lead plastic quad flatpack cy7c346-35rc/ri r100 100-pin windowed ceramic pin grid array cy7c346-35hmb h84 84-pin windowed leaded chip carrier military CY7C346-35RMB r100 100-pin windowed ceramic pin grid array ordering information (continued) speed (ns) ordering code package name package type operating range package diagrams 84-leaded windowed leaded chip carrier h84 51-80081-**
cy7c346 use ultra37000 tm for all new designs document #: 38-03005 rev. *b page 18 of 21 package diagrams (continued) 84-lead plastic leaded chip carrier j83 51-85006-*a
cy7c346 use ultra37000 tm for all new designs document #: 38-03005 rev. *b page 19 of 21 package diagrams (continued) 100-lead plastic quad flatpack n100 51-85052-*a
cy7c346 use ultra37000 tm for all new designs document #: 38-03005 rev. *b page 20 of 21 ? cypress semiconductor corporation, 2004. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress semiconductor product. nor does it convey or imply any license unde r patent or other rights. cypress semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected t o result in significant injury to the user. the inclusion of cypress semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in do ing so indemnifies cypress semiconductor against all charges. max and warp are registered tra demarks and ultra37000, warp professional and warp enterprise are trademarks of cypress semiconductor corporation. all product and company names mentioned in this documen t are the trademarks of their respective holders. package diagrams (continued) 100-pin windowed ceramic pin grid array r100 51-80010-*c
cy7c346 use ultra37000 tm for all new designs document #: 38-03005 rev. *b page 21 of 21 document history page document title: cy7c346 128-macrocell max? epld document number: 38-03005 rev. ecn no. issue date orig. of change description of change ** 106270 04/23/01 szv change from spec number 38-00244 to 38-03005 *a 113614 04/11/02 oor pga package diagram dimensions updated *b 213375 see ecn fsg added note to title page: ?use ultra37000 for all new designs?

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